Cache memory exchange protocol

Details Cache memory exchange protocol Cache memory exchange protocol

G - Physics

06

F

G06F 12/02 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2042515

A cache memory exchange protocol that utilizes an exchange memory access request is provided. A cache controller issues the exchange request over a system bus to a main memory in response to a cache miss if the cache location is dirty. Upon receiving the request, the main memory decodes the request and fetches a block of information desired by the CPU. While the main memory is fetching, the controller transfers a dirty cache block of information over the system bus and stores the dirty block in a temporary register located in the main memory. The block of information desired by the CPU is thereafter trans- ferred by the main memory to the CPU via the system bus. The dirty cache block residing in the temporary register is then stored in the main memory storage elements.

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