Cache memory having self-error checking and sequential...

Details Cache memory having self-error checking and sequential... Cache memory having self-error checking and sequential...

G - Physics

06

F

354/224

G06F 11/00 (2006.01) G06F 11/07 (2006.01) G06F 11/267 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1297193

NE-132-MK (046A/M4) "Cache Memory Having Self-Error Checking and Sequential Verification Circuits" ABSTRACT OF THE DISCLOSURE A multilevel cache memory system comprises a pseudo-error indicating flag for storing a first logic state when the system is in a normal error checking mode and a second logic state when the system is in a pseudo-error verification mode. A plurality of first logic gate circuits, associated respectively with the levels of the cache memory, are arranged to be disabled in response to the first logic state and enabled in response to the second logic state. A register having a plurality of stages corresponding in number to the levels of the cache memory stores level-invalidating data. A plurality of second logic gate circuits are associated respectively with the register stages for sequentially activating one of the first logic gate circuits in accordance with logic states of the register stages when the first logic gate circuits are enabled. A plurality of second flags are associated respectively with the first logic gate circuits to give an error indication in response to the activated first logic gate circuits.

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