Cache memory location selection mechanism

G - Physics – 11 – C

Patent

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354/246

G11C 7/00 (2006.01) G06F 12/12 (2006.01)

Patent

CA 1121515

52E2711 ABSTRACT Apparatus and method for improving the operation of the assignment of the cache memory locations for data to be utilized by the central processing unit. In normal operation, sequential assignment of memory locations can designate a memory location which is unavailable for data storage, causing the reassignment of the data to the next storage location in the sequence. This potential multiple step assignment process can be eliminated by simultaneous examination of status signals, indicating memory location availability, and signals, identifying the last assigned memory location, to provide the next available memory location in the memory location sequence. -2-

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