Cache-memory management unit system

Details Cache-memory management unit system Cache-memory management unit system

G - Physics

06

F

354/246

G06F 12/08 (2006.01) G06F 9/38 (2006.01) G06F 12/10 (2006.01)

Patent

CA 1272301

ABSTRACT A cache and memory management system architecture and associated protocol is disclosed. The cache and memory management system is comprised of a set associative memory cache subsystem, a set associative translation logic memory subsystem, hardwired page translation, selectable access mode logic, and selectively enablable instruction prefetch logic. The cache and memory management system includes a system interface for coupling to a systems bus to which a main memory is coupled, and is also comprised of a processor/cache bus interface for coupling to an external CPU. As disclosed, the cache memory management system can function as either an instruction cache with instruction prefetch capability, and on-chip program counter capabilities, and as a data cache memory management system which has an address register for receiving addresses from the CPU, to initiate a transfer of defined numbers of words of data commencing at the transmitted address. Another novel feature disclosed is the quad-word boundary, quad-word line registers, and quad-word boundary detector subsystem, which accelerates access of data within quad word boundaries, and provides for effective prefetch of sequentially ascending locations of storage instructions, or data from the cache memory subsystem.

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