Cache memory using a lowest priority replacement circuit

Details Cache memory using a lowest priority replacement circuit Cache memory using a lowest priority replacement circuit

G - Physics

06

F

354/244

G06F 12/12 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1175156

CACHE MEMORY USING A LOWEST PRIORITY REPLACEMENT CIRCUIT Abstract A data processing system having a processor, main memory, and a cache memory system which implements the earliest prior use replacement algorithm in replacing cache memory words with main memory words. The cache memory system is comprised of a cache control circuit and a plurality of cache memories. Each cache memory stores cache memory words having a similar time usage history. The first cache memory contains cache memory words which were more recently used than the cache memory words in the second cache memory, and the second cache memory contains cache memory words which were more recently used than the cache memory words in the third cache memory. When a main memory word must be transferred to the cache memory, the main memory word is stored in the first memory; and the first cache memory word having had the earliest prior use is stored in the second cache memory, etc. These operations maintain the proper time usage history of the cache memories.

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