G - Physics – 06 – F
Patent
G - Physics
06
F
354/246
G06F 13/00 (2006.01) G06F 12/04 (2006.01) G06F 12/08 (2006.01)
Patent
CA 1143860
ABSTRACT OF THE DISCLOSURE A cache organization that enables many cache func- tions to overlap without extending line fetch or line castout time and without requiring a cache technology faster than the main storage transfer rate. Main stor- age has a data bus-out and a data bus-in, each trans- ferring a double word (DW) in one cycle. Both buses may transfer respective DWs in opposite directions in the same cycle. The cache has a quadword (QW) write register and a QW read register, a QW being two SWs on a QW address boundary. During a line fetch (LF) of 16 DWs, either the first pair of DWs, or the first DW of the LF is loaded into the QW write register, depending on whether the first DW is on a QW address boundary or not, i.e., whether the fetch request address bit 28 is even or odd, respectively. Thereafter during the LF, the even and odd DWs are formed into QWs as received from the bus-out, and the QWs are written into the cache on alternate cycles, wherein no QW cache access occurs on the other alternate cycles for the LF. Either 8 or 9 QWs occur for a LF depending on the first DW boundary alignment. For a LF with 9 QWs, a write inhibit is needed for a non-data odd DW position in the last QW to avoid destroying the first DW written in the cache. If a line castout (CO) is required from the same or a different location in the cache, the CO can proceed during the alternate non-write cycles of any LF. Any cache bypass to the processor during the LF can over- lap the LF and CO. Any alternate cycles during any LF, which are not used for a CO or LF bypass, are available for processor request accesses of the cache for either DWs or QWs. PO9-79-006
360343
Messina Benedicto U.
Silkman William D.
International Business Machines Corporation
Saunders Raymond H.
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