G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 12/02 (2006.01) G06F 12/08 (2006.01)
Patent
CA 2357085
If a cache miss occurs at a time of a load request from a processor core, an issuance check block (20) issues a request of reading out data caused by the cache miss, to a main memory from an issuance control circuit (50), and then registers the information of the request in a request buffer circuit (30). A cache block (10) does not update an address array (12) at that time, and it is processed as a cache hit if a following instruction is hit to an address stored in an entry of an update schedule. The update of the address array (12) is done simultaneously with the update of a data array (11) when responsive data is received from the main memory with regard to said request. Accordingly, it is possible to provide a new cache update method, in which the feature of a cache of a non-blocking type can be sufficiently used, such as the merit of continuing a process for a following instruction even while the request of reading out the data caused by the cache miss is sent to the main memory.
Corporation Nec
Smart & Biggar
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