Cache with at least two different fill sizes

Details Cache with at least two different fill sizes Cache with at least two different fill sizes

G - Physics

06

F

354/241

G06F 12/12 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1314107

ABSTRACT A method and apparatus for optimizing the performance of a cache memory system is disclosed. During the operation of a computer system whose processor is supported by virtual cache memory, the cache must be cleared and refilled to allow the replacement of old data and instructions with more current instructions and data. The cache is filled with either P or N blocks of data. Numerous methods for dynamically selecting N or P blocks of data are possible. Pursuant to one embodiment, immediately after the cache has been flushed, the miss is refilled with N blocks, allowing data and instructions to be moved to the cache at high speed. Once the cache is mostly full, the miss tends to be refilled with P blocks, which is less than N. This maintains the currency of the data in the cache, while simultaneously avoiding writing-over of data or instructions already in the cache. The invention is particularly advantageous in a multi-user/multi-tasking system where the program being run changes frequently, necessitating flushing and clearing the cache frequently.

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