Cached multiprocessor system with pipeline timing

Details Cached multiprocessor system with pipeline timing Cached multiprocessor system with pipeline timing

G - Physics

06

F

354/233

G06F 9/00 (2006.01) G06F 15/00 (2006.01)

Patent

CA 1152222

ABSTRACT OF THE DISCLOSURE A pipelined multiprocessing system including a main core memory and a shared write-through cache memory that maintains readily accessible copies of data in the main core memory. A com- mon control unit (CCU) receives commands from the processors in a pipelined fashion thereby to control data transfers between the cache memory and the multiple processors, as well as between the cache memory and the main core memory in an ordered pipeline se- quence. The CCU also performs updating and allocating operations of the cache memory located therein. To improve data through put while sharing the cache memory, each processor connects to the CCU via a split-phase, bifurcated synchronous bus that carries address control signals in one phase and memory data signals in a differ- ent phase. Since write commands do not immediately alter the cache memory, the CCU also includes a Processor Index RAM (PIR) for tempor- arily storing addresses sought to be written by each of the respect- ive processors. When a processor issues a read command, it checks the contents of the PIR, and if the address sought to be read is one for which there is a write in progress by another processor, the CCU queues the read command for a subsequent access to the main core memory. The CCU also includes a duplicate tag store that maintains a copy of the cache memory tag addresses so that the cache memory can be updated without the necessity to pipeline all write returns through the CCU to update the cache memory when writing data to the main core memory.

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