Calibrated automatic test system

Details Calibrated automatic test system Calibrated automatic test system

G - Physics

01

R

324/3, 324/58.1

G01R 31/28 (2006.01) G01R 31/319 (2006.01)

Patent

CA 1273678

CALIBRATED AUTOMATIC TEST SYSTEM ABSTRACT A calibrated automatic test system includes a test station for generating digital test function codes and a test head containing a plurality of I/O pins for connection to a device under teat. Each 1/O pin includes a pin electronics circuit responsive to the digital test function codes for providing test signals to the device under test. The pin electronics circuits are inexpensive CMOS IC's and lack the accuracy needed to test VLSI devices at the frequencies of interest. An external calibration unit is connected to each I/O pin and data measurements are taken which represent the performance of the CMOS IC's. The data measurements are converted to calibrated function codes representing desired data values which are then stored in correction memory circuits which respond to nominal digital test function codes and substitute in their places cali- brated function codes which are then supplied to the pin electronics circuits.

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