Channel decoder and method of channel decoding

H - Electricity – 03 – M

Patent

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Details

H03M 13/29 (2006.01) H03M 13/45 (2006.01) H04L 1/22 (2006.01)

Patent

CA 2317202

There is disclosed a channel decoder for data encoded by serially concatenated outer and inner codes in which the outer code is a rate 1:2 repetition code operative to encode a data bit b n as two identical coded bits bcoded,n 0,bcoded,n 1, and in which the coded bits are interleaved. The decoder comprises a soft input soft output (SISO) inner decoder for which the input and output information are log likelihood ratios, input information being the log likelihood ratios of the encoded data and outer extrinsic information. Means are provided for subtracting feedback outer extrinsic information from the inner decoder information to produce inner extrinsic information. Means are also provided for swapping the log likelihood ration L n0,L n1, in the inner extrinsic information, corresponding to one information bit b n to produce the feed back extrinsic information. The coder is operative iteratively with outer extrinsic information produced by previous iterations. The pairs, corresponding to one data bit b n, of log likelihood ratios L n0,L n1, of the inner extrinsic information are summed, and a hard decision is based or the summed log likelihood ratios. The arrangement is especially simple compared with other decoders proposed in the prior art, especially when it is realised that the means for swapping can perform the swap without separate steps of deinterleaving and interleaving.

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