Channel interface circuit

Details Channel interface circuit Channel interface circuit

H - Electricity

04

L

340/84

H04L 5/14 (2006.01) G06F 13/28 (2006.01) G06F 15/16 (2006.01) G06F 15/167 (2006.01) G06F 12/02 (2006.01)

Patent

CA 1171931

CHANNEL INTERFACE CIRCUIT Abstract The subject channel interface circuit functions to provide a high speed interface between a processor and a data link, which link carries data messages having virtual addresses. The message handler is programmable and serves to translate the header portion of the data message from a virtual address into a hardware memory address, which is used to activate a specific location in the processor memory. The data portion of the data message is then directly inputted to this memory location (i.e., DMA) and the appropriate file pointers are reset. When a complete file is received and stored in memory, the message handler generates a processor interrupt. Thus, the subject message handler performs all the data receiving tasks, including file storage and linking, without requiring the involvement of the associated processor. All known prior art message handler circuits require extensive processor involvement in the data storage operation and thereby significantly reduce the effective data transfer capabilities of the link.

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