Charge-coupled area array

Details Charge-coupled area array Charge-coupled area array

G - Physics

11

C

345/1, 350/54

G11C 11/40 (2006.01) G11C 19/28 (2006.01) H01L 27/148 (2006.01) H01L 29/78 (2006.01) H04N 3/15 (2006.01)

Patent

CA 1049652

Application for Patent of Lloyd R. Walsh and James M. Early for CHARGE-COUPLED AREA ARRAY Abstract of the Disclosure A charge-coupled area array comprises a two-phase, buried channel semiconductor charge-coupled device (CCD) array which combines vertical CCD shift registers interdigitated and distinct from columns of light-sensing CCD elements. Two electrically isolated levels of doped polycrystalline silicon are utilized for the gate electrode structures of the CCD shift register elements and the light-sensing CCD elements of the array, Both of the doped polycrystalline gate electrode layers (vertical transport gates and frame gates) cooperate with barrier semiconductor regions of the array to permit bits of information (charge packets) generated in the light-sensing CCD elements to be laterally transported into the vertical CCD shift registers associated with the light-sensing CCD elements. One of the doped polycrystalline silicon gate electrode layers (vertical transport gates) is used to provide clock pulses to vertically move the charge packets within the shift register CCD elements of the array. These semiconductor barrier regions are of the same conductivity type as the buried region used to transport charge packets in the array. Insulating layers including silicon nitride are used to electrically insulate the semiconductor surface and the doped polycrystalline silicon gate electrode layers from each other.

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