Charge coupled memory device

G - Physics – 11 – C

Patent

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Details

356/12, 352/82.3

G11C 11/40 (2006.01) H01L 23/535 (2006.01) H01L 27/08 (2006.01) H01L 27/108 (2006.01)

Patent

CA 1137220

Abstract of the Disclosure A monolithically integrated semiconductor arrangement is disclosed wherein a plurality of first lines are provided which run parallel to one another and which are provided with first terminals at one end. A plurality of second lines which run parallel to one another are also provided which cross beneath the first lines and are connected via load elements at one end to a supply voltage terminal. Reference potential lines are also provided adjacent each of the second lines. At a series of selected crossing points of the first and second lines coupling elements are formed which can be operated by the first line and by which the second line id connected to an adjacent reference potential line. The semiconductor arrangement is formed on a semi- conductor layer having a thin insulating layer thereon with the second lines and reference potential lines arranged on the thin insulating layer. The first lines are then arranged over the second lines and reference potential lines and are separated therefrom by an additional insulating layer. At crossing points selected for coupling, a portion of the first line approaches the semiconductor layer surface more closely and is separated therefrom by the thin insulating layer. Diffusion zones are provided at one end of each of the reference potential lines and second lines. With the system disclosed, diffusions are not required for the formation of the first and second lines and coupling elements.

310611

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