Charge injection transistor memory

Details Charge injection transistor memory Charge injection transistor memory

G - Physics

11

C

352/82.3

G11C 11/40 (2006.01) G11C 11/404 (2006.01) H01L 27/07 (2006.01) H01L 27/102 (2006.01) H01L 29/78 (2006.01)

Patent

CA 1097813

CHARGE INJECTION TRANSISTOR MEMORY Abstract of the Disclosure Disclosed is a dynamic memory cell storing digital information, particularly adapted for integrated semi- conductor circuit fabrication. The circuit configuration has a bipolar transistor with information storage prefer- ably in the capacitance of the junctions, and a field effect transistor (FET) for selectively injecting charge into the capacitances. In integrated form, isolation is required only between columns of cells, a buried subcol- lector forming a common sense line for the entire column, while each of the base regions (also used as a first con- trolled region of the FET) requires no external contact at all. A further impurity region formed into each column of cells forms a second region of the FET and can be used as a bit line for the entire column. In one embodiment, separate contacts are provided for each of the emitter regions and each of the FET gate regions, while in another embodiment, only a single contact to both of the emitter region and FET gate region of each cell is required. FI9-75-042

272249

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