Charge redistribution mu-law pcm decoder

H - Electricity – 03 – M

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354/98

H03M 1/68 (2006.01)

Patent

CA 1193019

CHARGE REDISTRIBUTION MU-LAW PCM DECODER Abstract of Disclosure A mu-law PCM decoder requiring a total capacitance of only 32 times the normalized capacitance Co of the smallest capacitor thereof. The decoder comprises a source of positive and negative reference voltages, a differential input operational amplifier having its non-inverting input connected to ground, a storage capacitor CO=16Co connected as a feedback capacitor between the inverting input and the output terminals of the amplifier so that they operate as a voltage source, binary weighted capacitors Cl=Co, C2-2Co, C3=4Co and C4=8Co, and a second unit weighted capacitor C5=Co. Switch means alternately connect one and other sides of C1-C5 (1) between ground and either a + reference voltage or ground, in accordance with the characterizations in a PCM coded digital input word, and (2? across the storage capacitor CO for redistributing charge on the capacitors for each segment of the designated polarity. The resultant analog signal established on CO in the eighth segment is sampled prior to resetting the charge voltage on CO to substantially zero volts and receipt of the next PCM input word. Connections of plates of integrated capacitors and electrodes of switching transistors to ground and terminals of voltage sources renders the decoder substantially insensitive to stray and parasitic capacitance effects associated with the integrated capacitors and switches.

411584

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