Charge transfer memory

Details Charge transfer memory Charge transfer memory

G - Physics

11

C

352/82.2

G11C 11/34 (2006.01) G11C 19/28 (2006.01) G11C 19/36 (2006.01) H01L 27/105 (2006.01) H01L 29/423 (2006.01)

Patent

CA 1070015

Abstract Output gate electrode structure between the storage matrix and the output register of a serial-parallel-serial (SPS) charge coupled device (CCD) memory. To permit high channel packing density in the matrix, the output register can have as few as M/N stages, where M is the number of channels in the matrix and N the number of phases employed for operating the register, The gate structure transfers 1/N'th of a word at a time to the output register and while this 1/N'th of a word is being propagated out of the register, the remaining part (or parts), if any, of the word are stored while the gate structure provides a potential barrier between this stored charge and the register.

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