Check circuit for synchronized clocks

Details Check circuit for synchronized clocks Check circuit for synchronized clocks

G - Physics

06

F

354/231, 328/88,

G06F 1/04 (2006.01) H03K 5/26 (2006.01) H04M 3/24 (2006.01)

Patent

CA 1113575

CLOCK CHECK CIRCUITS USING DELAYED SIGNALS Abstract of the Disclosure In a data processing or transmission system which includes at least two synchronized clocks, for example - T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is period- ically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the indepen- dent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.

340653

Affiliated with

Also associated with

Rating

Check circuit for synchronized clocks does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Check circuit for synchronized clocks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Check circuit for synchronized clocks will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-865772