Chip interconnect with high density of vias

Details Chip interconnect with high density of vias Chip interconnect with high density of vias

H - Electricity

01

L

H01L 23/50 (2006.01) H01L 21/98 (2006.01) H01L 23/48 (2006.01) H01L 23/498 (2006.01) H05K 3/34 (2006.01)

Patent

CA 2074529

2074529 9111833 PCTABS00006 A solder interconnection for forming vias between first and second substrates (12, 14) comprises a plurality of solder containing wells (16) extending into a flat surface (18) of the first substrate (12), the solder (20) in each well (16) being soldered to one of a corresponding plurality of conductor posts (22) extending outwardly from a flat surface (23) of the second substrate (14). The plurality of the wells (16) are created in a pattern, an aliquot of solder (20) is deposited in each well (16), with the aliquot being of substantially no greater volume than that of the well (16) it occupies, the posts (22) are provided in aligned array with the pattern, the solder (20) is melted, the posts (22) are inserted and the solder (20) solidifies. Very closely placed vias can be formed.

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