Chip size package

Details Chip size package Chip size package

H - Electricity

01

L

H01L 23/02 (2006.01) H01L 23/32 (2006.01) H01L 23/495 (2006.01) H01L 23/498 (2006.01) H01L 23/58 (2006.01)

Patent

CA 2213542

A CSP (Chip Size Package) of the present invention includes a semiconductor IC (Integrated Circuit) chip having I/O (Input/Output) terminals along its edges. A small size substrate has a smaller contour than the chip and has a plurality of metal terminals arranged along the edges of its bottom, and a plurality of metal bumps arranged on its top in a lattice configuration. The top of the chip and the bottom of the substrate are so configured as to be electrically connected to each other via a tape member including a plurality of leads. These leads each includes a first terminal to be electrically connected to the associated I/O terminal of the chip, and a second terminal to be electrically connected to the associated metal terminal of the substrate.

Boîtier de la taille d'une puce (CSP) comprenant un circuit intégré à semi-conducteurs ayant des bornes d'entrée-sortie sur ses bords. Un substrat de petite taille, dont le périmètre est plus petit que celui de la puce, comporte un certain nombre de bornes métalliques sur les bords de sa surface inférieure et un certain nombre de bosses métalliques formant un treillis sur sa surface supérieure. Le dessus de la puce et le dessous de son substrat sont configurés de façon à être raccordés électriquement l'un à l'autre au moyen d'un élément d'une bande à conducteurs multiples. Ces conducteurs comprennent chacun une première borne destinée à être connectée à la borne d'entrée-sortie correspondante de la puce, et une deuxième borne destinée à être connectée à la borne métallique correspondante du substrat.

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