Chipset synchronization arrangement

Details Chipset synchronization arrangement Chipset synchronization arrangement

G - Physics

06

F

328/188

G06F 1/04 (2006.01) G06F 1/10 (2006.01) G06F 13/42 (2006.01)

Patent

CA 1200293

- 13 - CHIPSET SYNCHRONIZATION ARRANGEMENT Abstract Each chip of a microprocessor chipset is synchronized by an associated controller which adjusts a control signal for controlling the delay of a variable delay circuit during each operating cycle. The controller tailors the control signal for each chip by an op-amp which compares the output of an internal clock in each chip with a reference system voltage.

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