H - Electricity – 03 – K
Patent
H - Electricity
03
K
328/87
H03K 21/10 (2006.01) G06F 1/04 (2006.01) H03K 23/70 (2006.01)
Patent
CA 1283175
CIRCUIT AND METHOD FOR PERFORMING EQUAL DUTY CYCLE ODD VALUE CLOCK DIVISION AND CLOCK SYNCHRONIZATION Abstract of the Disclosure A circuit for dividing a master clock by an odd integral value and producing a 50% duty cycle. A state machine develops set and clear signals which are of a timing proportion of n: n + 1, where 2n + 1 is the divisor value. The set signal is provided to one input of a bistable multivibrator or S-R latch to set the multivibrator to a given state, while the clear signal is combined with the master clock signal to delay or disable the clearing of the multivibrator by 1/2 count of the master clock, so that an n + 1/2: n + 1/2 proportion output clock signal is developed. Additionally, the circuit includes a state machine which determines which of a series of differing frequency master clock signals is active and when an external triggering event occurs so that the following rising edge of the output clock signal is delayed until a determined time after the triggering event to allow synchronization of the output clock signal.
565673
Compaq Computer Corporation
Smart & Biggar
LandOfFree
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