Circuit and method for phase error cancellation in frequency...

Details Circuit and method for phase error cancellation in frequency... Circuit and method for phase error cancellation in frequency...

H - Electricity

03

L

H03L 7/18 (2006.01) H03K 23/66 (2006.01) H03L 7/081 (2006.01) H03L 7/197 (2006.01)

Patent

CA 2480258

A frequency divider circuit (11) has an input port for an input signal (FO) to be divided, an output port for a divided signal (FDIV), and means (12-19) for providing a variable division ratio control signal (N+C) and a residual quantization error signal (R), applying the variable division ratio control signal (N+C) to a control port of the frequency divider, and using the residual quantization error signal (R) to cancel phase error in the divided signal. Both the variable division ratio control signal (N+C) and the residual quantization error signal (R) are dithered.

L'invention concerne un circuit diviseur de fréquence (11) comprenant un port d'entrée destiné à un signal d'entrée (F<SB>O</SB>) à diviser, un port de sortie destiné à un signal divisé (F<SB>DIV</SB>), et des moyens (12-19) permettant d'obtenir un signal de commande à rapport de division variable (N+C) et un signal d'erreur de quantification résiduel (R), d'appliquer le signal de commande à rapport de division variable (N+C) à un port de commande du diviseur de fréquence, et d'utiliser le signal d'erreur de quantification résiduel (R) pour annuler l'erreur de phase dans le signal divisé. Le signal de commande à rapport de division variable (N+C) et le signal d'erreur de quantification résiduel (R) sont tous deux soumis à une diffusion d'erreur.

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