Circuit and method for processing scheduling

Details Circuit and method for processing scheduling Circuit and method for processing scheduling

H - Electricity

04

L

H04L 12/56 (2006.01) G06F 17/30 (2006.01)

Patent

CA 2315447

A scheduling processing circuit and a scheduling processing method can realize output objective queue determination process certainly and in short period. A packet communication system includes a plurality of network output ports and a plurality of port output queues provided corresponding to respective of the plurality of network output ports and holding packets determined the network output ports, for performing scheduling process of packet output timing. In such packet communication system, the scheduling processing circuit has storage means for storing output reservation flags in respective entries indicative of output reservation per address corresponding to respective of plurality of network output ports, and determining means for determining the network output port by retrieving the storage means on the basis of retrieval key word externally provided. The packet is read out for outputting from a port output queue corresponding to network output port determined by the determining means.

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