Circuit and method for split bias enable/inhibit memory...

G - Physics – 11 – C

Patent

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330/21, 352/41.1

G11C 11/40 (2006.01)

Patent

CA 1238413

CIRCUIT AND METHOD FOR SPLIT BIAS ENABLE/INHIBIT MEMORY OPERATION ABSTRACT OF THE DISCLOSURE A circuit and method for enabling/disabling a differential signal output from a memory device, such as a bipolar static random access memory, is disclosed. A split bias, current steering circuit includes a first differential amplifier for steering a current ID along a first current path when a first selected differential input signal, corresponding to a first logic state, is coupled to a first input terminal of said first differ- ential amplifier; and includes a second differential amplifier for steering current ID along a second current path when a second selected differential input signal, corresponding to a second logic state, is coupled to a second input terminal of said second differential ampli- fier. An output stage produces a selected logic output signal according to which of said first and second cur- rent paths is selected to steer current ID. A split bias enable/inhibit stage provides controlled operation of the first and second differential amplifiers. Cir- cuit operation is inhibited by splitting a bias signal supplied to the differential amplifiers. When inhibited, the circuit steers current ID along a predetermined one of said first and second current paths. This produces a corresponding continual predetermined logic output signal without regard to the differential input signal present at the first and second input terminals. Cir- cuit operation is enabled by balancing the bias signal supplied to the differential amplifiers. When enabled, both differential amplifiers connected to the output stage are operative.

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