H - Electricity – 02 – J
Patent
H - Electricity
02
J
H02J 7/00 (2006.01)
Patent
CA 2396105
The invention relates to a circuit arrangement that is provided with a chain (1) consisting of double layer capacitors (2). Modules (3) are connected in parallel in relation to the double layer capacitors (2). The impedance of said modules is reduced when the voltage above one of the double layer capacitors (2) exceeds a predetermined value. Overvoltages on the double layer capacitors (2) are thus effectively suppressed.
L'invention concerne un circuit qui comporte une chaîne (1) constituée de condensateurs à double couche (2). Parallèlement à ces condensateurs à double couche (2) sont montés des modules (3) dont l'impédance diminue quand la tension dépasse une valeur prédéterminée au niveau d'un des condensateurs à double couche (2). Ainsi des surtensions sont empêchées efficacement au niveau des condensateurs à double couche (2).
Kammerer Michael
Staib Bernd
Epcos Ag
Fetherstonhaugh & Co.
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