Circuit arrangement for controlling a solid state element

Details Circuit arrangement for controlling a solid state element Circuit arrangement for controlling a solid state element

G - Physics

05

F

328/193, 323/4

G05F 1/44 (2006.01) H03K 17/56 (2006.01) H03K 17/689 (2006.01)

Patent

CA 1210059

- 9 - Abstract of disclosure In order to have with an integratable solid state relay a galvanic isolation between the control and the switch similar to that of a mechanical relay the control is performed via DC/DC-converters in a classical voltage-doubler cir- cuit configuration. The switch function is provided by a pair of complementary MOS-transistors (Tr1 and Tr2) the gate/source capacitances (Cgs) of which are used as charging capacitances of the DC/DC-converters. In order to have a perfect blocking of the MOS-switches two DC/DC-converters (C1,C2,D1,D2,Cgs; C3,C2,D3,D5,Cgs) are provided which are controlled by two signals in phase opposition so that for both switching states the same noise margin capability and the same switching-over times result. The circuit arrangement includes only diodes, MOS-transistors and capacitances (C1,C2,C3) of very small value which can be integrated without any difficulties.

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