Circuit arrangement for distributing on-chip generated test...

Details Circuit arrangement for distributing on-chip generated test... Circuit arrangement for distributing on-chip generated test...

H - Electricity

01

L

H01L 21/66 (2006.01) G01R 31/3185 (2006.01)

Patent

CA 2086612

- 6 - Abstract A circuit arrangement for distributing on-chip generated test patterns with at least one scan path is described. With this arrangement, dependencies between individual test patterns are eliminated with the aid of networks of exclusive-OR gates (EO) between different scan path stages (Z). With this arrangement it is poss- ible to apply individual, very productive test patterns specifically to certain circuit components (K) and to eliminate linear dependencies between test patterns in a targeted manner. Significant Figure 1

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