Circuit arrangement for mitigating power switch capacitance

Details Circuit arrangement for mitigating power switch capacitance Circuit arrangement for mitigating power switch capacitance

H - Electricity

02

P

H02P 7/00 (2006.01) H02M 3/156 (2006.01) H02P 25/08 (2006.01) H03K 17/16 (2006.01)

Patent

CA 2129335

A circuit arrangement is provided to mitigate the parasitic capac- itance that typically is associated with solid state switches which are de- signed to carry high current magnitudes. By disposing a capacitive com- ponent in series with a power switch which, in turn, is connected in series with an inductive component, the overall capacitance of the switch and capacitive component are significantly reduced. In a preferred em- bodiment of the present invention, the capacitive component is a diode with a voltage potential provided at the cathode of the diode so that the parasitic capacitance of the diode can be varied to tune the total circuit for the purpose of achieving a specific resonant frequency. In applica- tions where high frequency signals are injected into the circuit for pur- poses of measuring a parameter, such as rotor position, the present in- vention is beneficial because of the ability to tune the frequency resulting from the residence of the series LC circuit which comprises a conductive component, such as a motor stator winding; and a capacitive compo- nent,such as a power switch which possesses an inherent parasitic cap- acitance. Another benefit of the present ivention is the fact that it makes possible the use of smaller components in a snubber network associated with the inductive component because of the increase in resonant fre- quency achieved by the decrease in capacitance of the series LC circuit.

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