Circuit arrangement for processing an atm cell overhead

Details Circuit arrangement for processing an atm cell overhead Circuit arrangement for processing an atm cell overhead

H - Electricity

04

Q

H04Q 11/04 (2006.01) H04L 12/56 (2006.01)

Patent

CA 2367578

In current transmission systems, information is transmitted in ATM cells which are conveyed using several channels (SDH). In prior art, a processing circuit can be provided for each channel, in which test information that is representative of the cell overhead is generated, evaluated or corrected. The invention reduces the number of processing circuits by connecting FIFO memory units to said circuits. The memory units record the information concerning the cell overhead and feed said information to the processing circuits, in such a way that one processing circuit processes the cell overhead of ATM cells from several channels.

Dans les systèmes de transmission actuels, des informations sont transmises dans des cellules MTA qui sont acheminées sur plusieurs voies. En l'état actuel de la technique, chaque canal est associé à un circuit de traitement dans lequel une information de contrôle représentative de l'en-tête de cellule est générée, évaluée ou corrigée. Selon la présente invention, le nombre des circuits de traitement est réduit du fait que des dispositifs à mémoire FIFO, qui sont connectés en amont de ces circuits, recueillent des informations concernant l'en-tête de cellule et les acheminent jusqu'au circuit de traitement, si bien qu'un seul circuit de traitement traite l'en-tête de cellules MTA de plusieurs voies.

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