Circuit arrangement for sampling a ternary signal

Details Circuit arrangement for sampling a ternary signal Circuit arrangement for sampling a ternary signal

H - Electricity

03

K

328/171

H03K 5/156 (2006.01) H03M 5/16 (2006.01) H04L 25/24 (2006.01)

Patent

CA 1271531

PHD 85 328 14 21.4.1986 ABSTRACT: Circuit arrangement for sampling a ternary signal. In a circuit arrangement for sampling a ternary signal, this ternary signal is divided by amplitude decision circuits into two binary signals and the binary sub-signals are sampled at m-times the rate of the symbol clock. The binary samples of each sub-signal are shifted through a shift register having at least m stages and intermediately stored in a buffer store for one period of the symbol clock. With the aid of a logic circuit it is then determined in which regions of the buffer store accumulations of identical binary values occur. Regions in which the accumulations always re-occur - the number of occurrences is checked by means of counters - are considered to be eyes of the ternary signal. In each clock period of the symbol clock, a sample falling within the eye of the ternary signal is transferred from each buffer store at an output of the circuit with the aid of a gate circuit.

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