Circuit arrangement for testing a digital circuit

Details Circuit arrangement for testing a digital circuit Circuit arrangement for testing a digital circuit

G - Physics

01

R

324/58.1

G01R 31/28 (2006.01) G06F 11/27 (2006.01) G06F 11/277 (2006.01)

Patent

CA 1248178

ABSTRACT OF THE DISCLOSURE Circuit arrangement for dynamic real time testing of a synchronous digital circuit having a clock pulse input, a stimulus input and a circuit node at which a digital test ignal is produced after a time delay of T seconds relative to the time of receipt of a signal at the stimulus input. The arrangement includes a clock pulse generator for generat- ing clock pulses; a transmitter device connected to the clock pulse generator and including a counter for counting the clock pulses and a digital signal generator for generating a repro- ducible digital stimulus signal having a length corresponding to a predetermined count of the counter. The transmitter device is connected for coupling a number of clock pulses corresponding to the predetermined count of the counter to the clock pulse input of the digital circuit and for delivering the digital stimulus signal to the stimulus input of the digital circuit in synchronism with the clock pulses coupled to the clock pulse input. An analyzing device has a first input arranged for receiving the digital test signal from the digital circuit and a second input connected for receiving the same number of clock pulses coupled to the digital circuit. The analyzing device is arranged for compressing and analyzing the test signal for errors. A device is provided for imparting a time delay of .pi. seconds to the clock pulses received by the analyzing means. - 1 -

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