Circuit arrangement with a multiplexer

H - Electricity – 04 – J

Patent

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Details

H04J 3/02 (2006.01) H03F 3/45 (2006.01) H03F 3/72 (2006.01)

Patent

CA 2181635

To connect one out of N signal channels (K1, K2, KN) each having a signal line (L1, L2, LN) and a channel zero line (N1, N2, NN), where N is greater than one, to one input of a (differential) amplifier (1) whose circuit is referenced to an associated ground (SN), a one-out-of-N multiplexer (2) is provided having 3N switching paths (S11, S21, S31, S12, S22, S32, S1N, S2N, S3N), a first (S11, S12, S1N) of which serves to connect the N signal lines (L1, L2, LN) to said input, and a second (S21, S22, S2N) of which serves to advance the N channel zero lines (N1, N2, NN). The respective inputs of the switching paths of a third switching-path set (S31, S32, SN) are connected to the respective inputs of the switching paths of the second switching-path set (S21, S22, S2N), and the outputs of the latter are commoned to one input of an auxiliary (differential) amplifier (3). The outputs of the third switching-path set (S31, S23, S2N) are commoned to the output of the auxiliary (differential) amplifier, whose circuit is referenced to the ground (SN) of the (differential) amplifier (1).

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