Circuit arrangement with at least one input and one output...

Details Circuit arrangement with at least one input and one output... Circuit arrangement with at least one input and one output...

H - Electricity

04

Q

H04Q 11/04 (2006.01) H04L 12/56 (2006.01)

Patent

CA 2066567

A circuit arrangement, preferably for a coupling network component of a network node in a packet-switching data network, is disclosed which has a wide parallelization of the data packet signal by means of shift registers, so that it is possible to operate internally with a greatly reduced operating speed. In particular, an arrangement of the components on a single semiconductor wafer permits an especially wide bus, which can be constructed extremely advantageously with a surface-optimized floor plan.

Est décrit une circuit (1000, 2000) notamment pour un composant de réseaux de couplage d'un noeud de réseau dans un réseau de transmission de données par paquets, lequel circuit présente une large mise en parallèle du signal de paquet de données au moyen du registre à décalage (60), de manière à permettre un fonctionnement interne avec une vitesse notablement réduite. Une configuration spéciale des composants sur une seule tranche de semi-conducteurs (3000, 4000) permet un bus particulièrement large (20), lequel peut être monté de manière très avantageuse avec une utilisation optimale des surfaces (3000, 4000).

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