G - Physics – 01 – R
Patent
G - Physics
01
R
G01R 31/317 (2006.01) G01R 25/00 (2006.01) G01R 31/3185 (2006.01)
Patent
CA 2169616
A circuit configuration for measuring a phase difference between a reference signal and a clock signal includes a first shift register being clocked by the clock signal and having an input receiving the reference signal. A digital differentiator is connected downstream of the first shift register and has an output. A counter has an input receiving the clock signal and an output outputting a multidigit binary word. A buffer memory is connected to the counter and to the digital differentiator for storing the binary word at the output of the counter in memory upon an appearance of a corresponding output signal of the digital differentiator. The buffer memory has an output forming most significant bits of an output binary word. A second shift register is in- versely clocked by the clock signal and has an input receiv- ing the reference signal and an output. An analog differentiator has an input connected to the output of the digital differentiator and an output. A D flip-flop has a data input connected to the output of the second shift register and a clock input connected to the output of the analog differentiator for supplying an output signal forming a least significant bit of the output binary word.
Aktiengesellschaft Siemens
Fetherstonhaugh & Co.
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