Circuit for clock signal extraction from a high speed data...

Details Circuit for clock signal extraction from a high speed data... Circuit for clock signal extraction from a high speed data...

H - Electricity

04

L

H04L 7/033 (2006.01) H03L 7/113 (2006.01) H03L 7/14 (2006.01) H03D 13/00 (2006.01) H03L 7/087 (2006.01) H03L 7/089 (2006.01)

Patent

CA 2171690

A circuit for clock signal extraction from a high speed data stream for providing rapid locking with the input data stream and a locally generated clock signal. The circuit is suitable for fabrication in a CMOS digital integrated circuit, and features low power dissipation and is capable of operating at bit rates exceeding 300 Mbit/s. The circuit comprises a main phase locked loop, which controls a voltage controlled oscillator by continually controlling its phase, and a secondary loop, which allows the main loop to become locked, by causing the voltage controlled oscillator to oscillate at a frequency close to the operating frequency.

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