H - Electricity – 04 – J
Patent
H - Electricity
04
J
363/17
H04J 3/06 (2006.01)
Patent
CA 1264384
ABSTRACT The circuit of the invention detects/recognizes multi- frame synchronization bits of concurrently existing plural unknown kinds of multi-frame synchronization in a received signals of digital transmission. The abovementioned detection as well as recognition is carried out by software in place of wired logic of prior art. A micro processor instructs a gate to extract a specific bit out of received sequential bits. The extracted bit is inputted to a shift register and outputted therefrom after being delayed by the elapsing frame numbers via its respective output terminals corresponding to the delaying frame numbers. The out- putted bit is compared with a not-delayed inputted bit, and if they meet a predetermined format, the bit is recognized as being of a multi-frame synchronization. The bit extraction is scanned over all the control signal bits, and the results are stored in a memory. By use of thus stored information, the processor recog- nizes the existing types of the multi-frame synchronization. Furthermore, based on the thus stored information, the processor periodically monitors whether the synchronization is normal, and if it is stepping out, the synchronization detection procedure is repeated. The invention permits the recognization of mixed kinds of multi-frame synchronization to be achieved simply and without increasing the circuitry, because it can be done by programming of the micro processor.
549460
Fetherstonhaugh & Co.
Fujitsu Limited
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