Circuit for easily testing a logic circuit having a number...

Details Circuit for easily testing a logic circuit having a number... Circuit for easily testing a logic circuit having a number...

G - Physics

01

R

G01R 31/3177 (2006.01) G01R 31/3185 (2006.01)

Patent

CA 2223221

A scan path circuit is for use in testing a logic package designed in accordance with scan path fashion. The logic package comprises a logic circuit and a plurality of scan paths. The logic circuit has first through N-th input/output pins, where N represents a positive integer which is greater than one. The scan paths are connected in serial to one another and are connected to the logic circuit. The scan path circuit comprises first through N-th memory sections which are connected in serial to one another and which are connected to the first through the N-th input/output pins, respectively. Each of the memory sections comprises a first memory circuit and a second memory circuit. The first memory circuit of an n-th memory section supplies test input to an n-th input/output pin in a shifting mode, where n is a variable between one and N. The first memory circuit of the n-th memory section takes test output from the logic circuit through the n-th input/output pin in a normal mode. The second memory circuit of the n-th memory section holds test input in the shifting mode to prevent the test input from varying to a varied input.

Circuit à trajets de balayage servant à tester un ensemble logique conçu selon un modèle d'établissement de trajets de balayage. L'ensemble logique comprend un circuit logique et un certain nombre de trajets de balayage. Le circuit logique comprend un nombre N de broches d'entrée-sortie, où N représente un entier positif plus grand que un. Les trajets de balayage sont connectés en série entre eux et au circuit logique. Le circuit de trajet de balayage comprend un nombre N de sections de mémoire qui sont connectées auxdites N broches d'entrée-sortie, respectivement. Chacune des sections de mémoire comprend un premier et un second circuits de mémoire. Le premier circuit de mémoire d'une n-ième section de mémoire transmet une entrée d'essai à une n-ième broche d'entrée-sortie en mode décalage, n étant une variable comprise entre un et N. Le premier circuit de mémoire de la n-ième section de mémoire reçoit une sortie d'essai du circuit logique par l'intermédiaire de la n-ième broche d'entrée-sortie en mode normal. Le second circuit de mémoire de la n-ième section de mémoire maintient l'entrée d'essai en mode décalage afin de l'empêcher de varier.

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