Circuit for establishing accurate sample timing

Details Circuit for establishing accurate sample timing Circuit for establishing accurate sample timing

H - Electricity

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H04J 11/00 (2006.01) H04J 1/02 (2006.01) H04L 7/02 (2006.01) H04L 25/03 (2006.01) H04L 27/14 (2006.01) H04L 27/26 (2006.01) H04L 27/38 (2006.01)

Patent

CA 1224541

ABSTRACT "Circuit for Establishing Accurate Sample Timing" In order to establish accurate sample timing in a digital demodulator which forms part of an orthogonally multiplexed parallel data transmission system, two second-order PLLs are arranged after a demodulating section of the digital demodultor so as to receive baseband signals of corresponding pilot channels. The two second-order PLLs each includes an integrator. These integrators apply the outputs thereof to a subtracter which applies the subtraction result to a voltage-controlled oscillator in order to establish the accurate sample timing.

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