G - Physics – 06 – F
Patent
G - Physics
06
F
354/246
G06F 7/10 (2006.01) G06F 12/12 (2006.01)
Patent
CA 1059643
A CIRCUIT FOR IMPLEMENTING A MODIFIED LRU REPLACEMENT ALGORITHM FOR A CACHE Abstract of the Disclosure The invention operates with a storage hierarchy buffer such as a cache, with an LRU network which utilizes two array memory chips, array selection and addressing controls, chronology controls, next LRU addressing circuits, and mode controls for controlling the different types of operations needed by the LRU network. Each time a different block is accessed in the cache, a next use value is generated in a chronology register in the chronology controls, and the new use value is written into the active one of the arrays at a position which corresponds to the position of the block to be replaced in the cache. An LRU determination is made when a cache miss occurs by making a search of the active array to find the position of the block with the lowest use value, which block position is thus determined to be the LRU. This LRU block address is then stored in the next LRU addressing circuits for use by the next block replacement in the cache, i.e. next miss.
268655
Bryant Louis R.
Pedersen Raymond J.
Weinberger Arnold
International Business Machines Corporation
Na
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