Circuit for monitoring the square of the rms value of a...

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328/171

G01R 19/02 (2006.01) G01R 19/165 (2006.01) G06G 7/20 (2006.01) H02H 3/08 (2006.01)

Patent

CA 1143443

ABSTRACT A circuit arrangement for monitoring the square of the RMS value of a periodic signal in which an integrator following a squarer is reset to zero at periodic intervals. A first limit detector connected thereto deliv- ers, if the limit set therein is exceeded, a pulse which is fed, via a first conjunctive logic element, to the counting input of a counter. The counter delivers a continuous signal to an indicator and to the first conjunctive logic element when a preset counter reading is reached. A gate circuit blocks the periodic resetting of the counter as long as the first limit detector responds in each periodic time interval or when the preset counter reading is reached. This circuit permits quick determination of the RMS value.

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