H - Electricity – 03 – K
Patent
H - Electricity
03
K
328/71
H03K 27/00 (2006.01) H03K 23/50 (2006.01)
Patent
CA 1150367
ABSTRACT Disclosed is a circuit for odd frequency division of a given pulse train which provides an output pulse train having a duty ratio of fifty percent. For (2N-1) division (N is a plural number), N-delay type flip-flops are connected in cascade to form a shift register, each flip-flop having a signal input terminal for receiving a pulse train to be shifted, a clock input terminal for receiving a clock pulse train for shifting the pulse train at the signal input terminal, a non-inverting output terminal and an inverting output terminal. The output from the inverting terminal of the last flip-flop is fed back to the signal input terminal of the first flip-flop. An Exclusive OR circuit has a first input terminal for receiving a pulse train to be frequency-divided and a second input terminal for receiving a pulse train from the inverting or non- inverting output terminal of a predetermined flip-flop of the shift register. The Exclusive OR supplies a clock pulse train for frequency dividing to all the clock input terminals of the shift register so that first and second output pulse trains are produced from each of the flip-flops of the shift register.
373034
Nippon Electric Co. Ltd.
Smart & Biggar
LandOfFree
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