Circuit for reducing errors in a data receiver

Details Circuit for reducing errors in a data receiver Circuit for reducing errors in a data receiver

H - Electricity

04

B

325/120

H04B 15/00 (2006.01) H04L 27/233 (2006.01) H04L 27/38 (2006.01) H04L 27/00 (2006.01)

Patent

CA 1218116

-20- CIRCUIT FOR REDUCING ERRORS IN A DATA RECEIVER Abstract of the Disclosure In a data receiver, a complex data signal after demodulation and sampling is applied to an equalizer which provides an improved signal which is applied to a phase and amplitude correction circuit for correction utilizing a complex reference vector. The corrected signal is applied to a decision circuit the input and output of which are applied to a difference determinator circuit, the output of which is a complex residual error signal utilized in conjunction with a plurality of gain factors generated in a gain factors generator to deter- mine the reference vector. The gain factors vary in time from transmission initialization such that optimal compensation for transmission disturbances is achieved both at initialization and after stabilization.

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