Circuit to minimize local clock frequency disturbances when...

Details Circuit to minimize local clock frequency disturbances when... Circuit to minimize local clock frequency disturbances when...

H - Electricity

03

L

328/102, 354/231

H03L 7/14 (2006.01) H03L 7/10 (2006.01)

Patent

CA 1215436

TITLE CIRCUIT TO MINIMIZE LOCAL CLOCK FREQUENCY DISTURBANCES WHEN PHASE LOCKING TO A REFERENCE CLOCK CIRCUIT ABSTRACT OF THE DISCLOSURE A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse gen- erator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock cir- cuits. A window circuit provides a signal representa- tive of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interroga- tion by a microprocessor which causes a voltage con- trolled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

455943

Affiliated with

Also associated with

Rating

Circuit to minimize local clock frequency disturbances when... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit to minimize local clock frequency disturbances when..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit to minimize local clock frequency disturbances when... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1314002