Clock adapter using a phase locked loop configured as a...

Details Clock adapter using a phase locked loop configured as a... Clock adapter using a phase locked loop configured as a...

H - Electricity

03

L

328/28, 328/50,

H03L 7/18 (2006.01)

Patent

CA 2002382

A phase locked loop configured as a frequency multiplier capable of nonintegral feedback path division utilizes a multiphase voltage controlled oscillator (5) which generates plurality of signals (10a - 10f) having a substantially identical frequency but each offset equally from the other by a given phase angle. A commutator (3) selects signals of adjacent phases so as to give the time average output signal (9) a frequency higher of lower than the frequency 10a - 10f. Frequency translation is accomplished by periodically selecting signals having a longer or shorter period as desired so that a clock output signal is delayed or advanced by an appropriate amount. In the preferred embodiment, the clock adapter is capable of converting a 1.544 MHz signal to a 2.048 MHz signal or vice versa.

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