Clock circuit

Details Clock circuit Clock circuit

H - Electricity

03

K

328/87

H03K 5/135 (2006.01)

Patent

CA 1196065

CLOCK CIRCUIT ABSTRACT A clock generator circuit (10) receives an input signal PPC0 and generates a delayed clock output signal PC0. The circut (10) is set to an initial condition by a precharge signal PC0R prior to a transition of the input signal PPC0. A time delay signal is produced at a node (26) by operation of transistors (18, 28). The transition of the input signal PPC0 produces a bootstrapped voltage at a capacitor (68). The delay signal activates a transistor (80) to couple the bootstrapped voltage to the gate terminal of an output transistor (88). The gate terminal of the output transistor (88) is driven directly from a low voltage state to a boosted high voltage state. This causes the output signal PC0 to be driven from an initial low voltage state to the power supply voltage Vcc without intervening steps. The output transistors (88, 90) of circuit (10) are never activated at the same time, thereby preventing any current spike from being propagated through the circuit (10).

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