Clock circuit synchronization in digital transmission system

H - Electricity – 04 – L

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331/35, 331/58

H04L 7/02 (2006.01) H03L 7/07 (2006.01) H03L 7/08 (2006.01) H03L 7/14 (2006.01) H04J 3/06 (2006.01) H04L 7/00 (2006.01)

Patent

CA 1290824

- 29 - CLOCK CIRCUIT SYNCHRONIZATION IN DIGITAL TRANSMISSION SYSTEM Abstract Synchronization of a local timing signal (Ts) with an incoming reference timing signal (?i(t)) is realized by employing is realized by employing a frequency estimator and frequency synthesizer in conjunction with a local fixed oscillator. The frequency estimator includes a first phase-locked loop including an integrator for generating a frequency estimate which is the difference between the frequency of the incoming reference timing signal and the frequency of the fixed oscillator signal. The phase value (PHLOL(n)) of the frequency estimate (FRQEST(n)) obtained by integrating the frequency estimate is supplied to a second phase-locked loop which includes a digitally controlled oscillator to generate the local timing signal (?o(t)), If the incoming reference timing signal (?i(t)) is lost or if there is too large a variation in a phase error signal (PHIN(n)) in the first phase-locked loop, the value of the frequency estimate is held constant. Consequently, the second phase-locked loop never free runs and the local timing signal (?o(t)) remains in synchronization with the reference timing signal (?i(t)).

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