G - Physics – 06 – F
Patent
G - Physics
06
F
354/166, 354/231
G06F 1/14 (2006.01) G06F 1/10 (2006.01) G06F 9/302 (2006.01) G06F 11/07 (2006.01) G06F 15/80 (2006.01) G06F 11/20 (2006.01)
Patent
CA 2000378
Abstract of the Disclosure: In a computer system comprising first through K-th arithmetic processors connected to a control section (18) in an ascending order, where K represents a positive integer which is not less than two, a memorizing unit (20) memorizes first and second information. A clock controlling unit (21) detects a fault signal produced by a k-th arithmetic processor, where k represents one of 1 through K. When the memorizing unit memorizes the first information, the controlling unit controls a supplying unit (19) to put the k-th through the K-th arithmetic processors out of operation. When the memorizing unit memorizes the second information, the controlling unit controls the supplying unit to put the first through the K-th arithmetic processors out of operation even upon production of the fault signal by any one of the first through the K-th arithmetic processors. Besides a first group of the first through the K-th arithmetic processors, a second group may be included in the computer system to comprise an additional arithmetic processor connected to the control section. When the memorizing unit memorizes the first information, the additional arithmetic processor is kept in operation. When the memorizing unit memorizes the second information, the additional arithmetic processor is put out of operation.
Iwata Jun
Kasai Hiroyuki
Corporation Nec
Smart & Biggar
LandOfFree
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