Clock/data recovery circuit

Details Clock/data recovery circuit Clock/data recovery circuit

H - Electricity

04

L

H04L 7/027 (2006.01) H03L 7/08 (2006.01) H03L 7/097 (2006.01) H04J 3/04 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2374777

A clock/data recovery circuit used in a receiving apparatus is provided in the circuit including: a voltage control oscillator for generating a clock signal of a frequency of 1/K of a bit rate of an input data signal; a delay circuit; a demultiplexer for demultiplexing the input data signal; a multiplexer for multiplexing the demultiplexed signals; a phase comparator for comparing phases of an output signal of the delay circuit and an output signal of the multiplexer; a lowpass filter; wherein the clock/data recovery circuit outputs the clock signal generated by the voltage control oscillator as a recovery divided clock signal, and outputs the demultiplexed signals output as recovery parallel data signals.

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