Clock extracting circuit

Details Clock extracting circuit Clock extracting circuit

H - Electricity

04

L

340/205, 328/87

H04L 7/00 (2006.01) H03K 5/1532 (2006.01) H04L 7/02 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1172336

ABSTRACT OF THE DISCLOSURE A clock extractor is disclosed in which an input data signal is sampled and held in accordance with a sampling frequency, the input data signal thus processed is subjected to equalization and amplification, a dif- ference in voltage (namely, height) is detected between those portions of a waveform obtained after the equaliza- tion and amplification which appear before and after a time when the waveform has a maximum voltage amplitude, a phase of that portion of the waveform which has the maximum voltage amplitude, is determined by making the above-mentioned difference equal to zero, and a clock signal synchronized with the portion having the maximum voltage amplitude is extracted and reproduced from the input data signal.

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